The present invention relates to semiconductor integrated circuit devices including electro-static discharge (ESD) protection circuits, and particularly relates to semiconductor integrated circuit devices including silicon-controlled rectifier (SCR) protection circuits incorporated in ESD protection circuits.
With recent developments of technology in processing field, such as miniaturization and increase in density, semiconductor integrated circuit devices are more and more susceptible to damage from ESD (hereinafter, referred to as a surge). For example, there is an increasing possibility that a surge entering from an external connector pad destroys a device, such as an input circuit, an output circuit, an input/output circuit or an internal circuit, to cause degradation of device performance. Accordingly, the semiconductor integrated circuit devices include ESD protection circuits added to external connector pads and used for protecting input circuits, output circuits, input/output circuits and internal circuits against surges.
FIG. 13 illustrates a circuit configuration of a conventional semiconductor integrated circuit device including an ESD protection circuit (see, for example, Japanese translation of PCT international application No. 2004-531047). As illustrated in FIG. 13, the conventional semiconductor integrated circuit device includes: a power line 101, a ground line 102; an SCR protection circuit 103; a trigger circuit 104 connected to the SCR protection circuit 103 in parallel with each other; and a protected circuit 105 protected against surges and having a desired circuit function. The SCR protection circuit 103 is configured to protect the protected circuit 105 against surges entering from the power line 101 by making the surges flow into the ground line 102.
The SCR protection circuit 103 is provided between the power line 101 and the ground line 102 and is made of, for example, a pnp bipolar transistor and an npn bipolar transistor which share a connector and a base, as described with transistor symbols. The collector of the npn bipolar transistor serves as a trigger terminal 106.
The trigger circuit 104 is provided between the power line 101 and the trigger terminal 106 and includes an NMOS transistor 107 having its drain connected to the power line 101 and the source and gate connected to the trigger terminal 106 of the SCR protection circuit 103.
The protected circuit 105 is connected to the power line 101 and the ground line 102.
In the conventional semiconductor integrated circuit device having the foregoing configuration, upon application of a positive surge between the power line 101 and the ground line 102, the nMOS transistor 107 forming the trigger circuit 104 breaks down to cause a positive voltage to be applied to the trigger terminal 106, so that current (SCR trigger current) starts to flow from the trigger terminal 106 into the ground line. This SCR trigger current turns the SCR protection circuit 103 ON, so that a flow of current (latch-up phenomenon) is maintained at a very low ON resistance between the anode and the cathode of the SCR protection circuit 103. Accordingly, the protected circuit 105 is protected against a positive surge entering through the power line 101 from outside the device.
However, in the conventional semiconductor integrated circuit device, when a surge of positive charge is applied to the power line 101 with the ground line 102 grounded, the protected circuit 105 might be destroyed under miniaturization in processing.
This is because the thickness of a gate oxide film of a MOS transistor included in the protected circuit 105 is reduced with miniaturization in processing and, therefore, the breakdown voltage of the gate oxide film decreases, so that the ON voltage, which is determined according to the breakdown voltage of the nMOS transistor 107, of the SCR protection circuit 103 can be higher than the breakdown voltage of the gate oxide film of the transistor included in the protected circuit 105. That is, the potential at the power line 101 exceeds the breakdown voltage of the gate oxide film of the MOS transistor before the SCR protection circuit 103 turns ON, resulting in destruction of the gate oxide film of the transistor included in the protected circuit 105.